1. Field of the Invention.
The present invention relates generally to memory devices in computer systems. In particular, the present invention relates to a system and method for specifying operation of one or more of a plurality of memory devices by multicasting address signals to the plurality of memory devices.
2. Description of the Background Art.
There are a variety of interconnect architectures for connecting memory devices to a controller. Examples of such prior art approaches are shown in FIGS. 1A and 1B. The prior art often uses a memory controller to provide the coupling between a system bus and the memory devices (RAM). As shown in FIG. 1A, the memory controller can be coupled to the memory devices by a command and address bus for passing command and address signals, and a data bus for sending and receiving data from the system bus. Typical prior art systems also include a series of chip select signal lines. The chip select signal lines are used to selectively activate the memory device(s) for operation. However, one significant problem with this prior art approach is that the chip select signal lines have different physical properties (i.e., varying lengths). Therefore, in high performance memory systems, the different physical properties of each signal line affect the timing characteristics for the chip select and command signals. In other words, the skew between the chip select signals and the command signals places a fundamental limit on the speed at which the commands can be sent between a memory controller and its attached memory devices. This is a particular problem when high speed bus architectures are used. Further, the use of individual chip select lines requires the memory controller have a pin for each chip select line which increases the cost of the memory controller. Similarly, when memory modules such as Single In-Line Memory Modules (SIMMs) or Dual In-Line Memory Modules (DIMMs) are used it is not practical to provide a pin for each chip select of each memory in the SIMM. Such an approach would require eight pins just for the chip select input to a SIMM having eight memories. Also, unless a large number of pins for chip select lines are provided, the flexibility or ability to use the memory controller with varying number of memory device is limited. Furthermore, there have been attempts in the prior art to adjust or add components to make the physical properties the same for all lines. This is very difficult to accomplish when the physics of the chip select signal lines (which attach to only one memory chip) and the address signal lines (which attach to all memory chips) are inherently different.
Yet another prior art approach is shown in FIG. 1B, and more fully disclosed in U.S. Pat. No. 5,319,755 issued to Farmwald et al. FIG. 1B illustrates a memory controller coupled to the memory devices by a combined command, address and data bus. In this second prior art approach, one of the memory devices can be addressed or special transactions (like refresh) can be broadcast to all memory devices. While this approach does not suffer from the shortcomings of the approach in FIG. 1A, this second approach does not offer the flexibility of selecting groups of memory devices for operation. Further not all commands can be broadcast to groups of memory devices. For example, reads and other commands cannot be broadcast to the multiple memory devices because only one data bus is provided on which the memory devices can respond. Broadcast messages to the memory devices have been provided for this second approach, but they have been limited to clearing and refreshing the memory devices. Additionally, when memory modules (SIMMs, DIMMs, etc.) are used, the broadcast messages can only be used to select all memory modules and not an individual memory devices or an individual memory module for refreshing or clearing. Accessing an individual memory device is useful when only one byte is being modified. Accessing one memory module is useful for reading or writing a block of locations (a memory line), where each memory device contains a portion of that memory line. Both types of accesses are not possible with the prior art approach of FIG. 1B.
Thus, there is a continuing need for a system and method for selecting individual or groups of memory device for operation. This system and method should not require extensive hardware and be adaptable to a variety of memory architectures that include the use of memory modules.